Embedded speaker protection for automotive audio power amplifier

ABSTRACT

A circuit can be used in a speaker system. The circuit includes an amplifier with an output configured to be coupled to a speaker. An offset comparator has an input coupled the output of the amplifier and is configured to provide an offset control signal. A digital circuit has a first input coupled to an output of the offset comparator, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal that can be used to control the amplifier.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 15/158,854, filed May 19, 2016 (now U.S. Pat. No. 9,532,142), which is a division of U.S. application Ser. No. 14/754,861, filed Jun. 30, 2015 (now U.S. Pat. No. 9,386,372), which is a division of U.S. application Ser. No. 13/692,789, filed Dec. 3, 2012 (now U.S. Pat. No. 9,099,978), which claims the priority benefit of Chinese patent application number 201110461473.8, filed on Dec. 30, 2011, each of which is hereby incorporated by reference to the maximum extent allowable by law.

TECHNICAL FIELD

The present invention relates to audio speaker protection, and, more particularly to an embedded speaker protection method and circuit embodiment thereof for an automotive audio power amplifier, which can protect the speakers automatically in case of high offset during a turn-on procedure.

BACKGROUND

In automotive power amplifier devices an offset detector function is normally embedded. Any DC output offset exceeding .+−0.2V is signaled out no matter if there is an input signal or not. This abnormal offset, when there is no input signal, might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the input. The abnormal offset can put the speakers at risk of overheating, or damage the speakers directly.

In current applications of automotive audio power amplifiers, if an audio system is to protect the speakers in case of high output offset, an MCU (microprocessor) must first read the offset detector outputs from the amplifier, and put the amplifier in a mute mode if a high offset is detected. All these actions require extra MCU operations and are controlled outside of the power amplifier IC.

To read the information given by the power amplifier (for example in the TDA7563B quad power amplifier) the diagnosis has to be performed with a low-level output AC signal (or Vin=o). An MCU enables the offset detection by setting an I²C command IB1D<5>=1 and then reads the status of the amplifier after a selectable testing time. An excess offset greater than +/−2V is signaled out if it is persistent throughout the assigned testing time. The MCU then can decide to turn off or mute the power amplifier, or just do nothing.

If the MCU ignores all the operations described above, the power amplifier may maintain play mode with a high offset feeding to the speakers without any protections, which is undesirable for the reasons given above.

Referring now to FIG. 1, a flow chart 100 shows the turn-on sequence for the prior art amplifier described above. An MCU enables the offset detection, and sets the IBID<5> bit to a logic one at step 102. The MCU then reads the offset status at step 104. A decision block 106 asks whether or not the offset read is greater than two volts. If no, then the audio amplifier maintains its current working state at step 108. If yes, then the MCU sends a mute command to the amplifier, or simply turns the amplifier off at step 110.

Referring now to FIG. 2, a plot of the voltage at the two speaker output terminals 202 and 204 is shown in a turn-on procedure in the case of an abnormal offset without MCU intervention according to the prior art. The step function in traces 202 and 204 are caused by the abnormal offset in the speaker system.

What is desired is a more direct method and corresponding circuit apparatus for providing the prior art functionality more quickly, and without incurring the extra MCU cycles described above.

SUMMARY

According to the present invention a method of operating a speaker system including a speaker coupled to an amplifier, and a dedicated digital speaker protection circuit comprises turning on the amplifier in a mute mode, after a first delay period, issuing a play command to the amplifier to place the amplifier in a play mode, but without an input signal during a second delay period, and performing a speaker offset detection during the second delay period, wherein, if there is an offset, then the amplifier is forced back into the mute mode, and if there is no offset, then the amplifier is allowed to continue to operate in the play mode. A microprocessor issues a command to place the amplifier in the mute and play modes. The first delay period is about a second. And the second delay period is about 100 milliseconds. Forcing the amplifier back into the mute mode is accomplished by the dedicated digital circuit associated with the amplifier. The offset detection comprises a detection of a threshold offset greater than about two volts. The method of the present invention further comprises issuing a speaker protection control signal or command if an offset is detected.

A speaker system according to the present invention comprises a speaker coupled to an amplifier, an offset comparator coupled to the speaker for providing an offset control signal, a digital circuit having a first input coupled to an output of the offset comparator, a second input for receiving an amplifier control signal, a third input for receiving a play control signal, and an output for providing a forced mute signal, and a microprocessor for controlling the amplifier.

The digital circuit comprises an intermediate node for providing a speaker protection control signal, a first latch for receiving the offset control signal, a first logic gate for receiving the play control signal, the offset control signal, and the speaker protection control signal, a second logic gate coupled to the first latch for receiving the play control signal and the speaker protection control signal, a second latch coupled to the first logic gate for providing the forced mute signal, and a third latch coupled to the second logic gate and to the intermediate node. The first, second, and third latches are clocked by the amplifier control signal. The first, second, and third latches comprise D-type flip flops. The first and second logic gates comprise three-input NAND gates.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flowchart of a speaker protection procedure according to the prior art;

FIG. 2 is a plot of the voltage at the two speaker output terminals in a turn-on procedure in the case of an abnormal offset without MCU intervention according to the prior art;

FIGS. 3A and 3B taken together is a simplified circuit diagram for a dedicated digital speaker protection according to the present invention;

FIG. 4 is a flowchart of a speaker protection procedure according to the present invention; and

FIG. 5 is a plot of the voltage at the two speaker output terminals in which the amplifier is quickly muted after the detection of a high offset condition, according to the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

According to the present invention, a speaker protection function is embedded inside the power amplifier device itself, by means of a dedicated digital circuit.

A simplified circuit diagram for the digital circuit 340 that provides the speaker protection function is shown in FIGS. 3A and 3B, which is split into two parts for sake of clarity. The flip-flop enabling signal ON goes high when the amplifier is turned on. The FORCEMUTE signal goes to the reference block 330 to control the mute state of the whole amplifier 320. In the reference block 330, if FORCEMUTE is high, a low output is provided by the play/mute comparator 332.

A speaker system 300 includes a speaker 302 coupled to an amplifier, an offset comparator 304 coupled to the speaker for providing an offset control signal at node 305, a digital circuit (306, 308, 310, 312, 314) having a first input coupled to an output of the offset comparator 304, a second input for receiving an amplifier control signal (ON), a third input for receiving a play control signal at node 307, and an output for providing a forced mute signal (FORCEMUTE), and a microprocessor (MCU) for controlling the amplifier.

The digital circuit includes an intermediate node 309 for providing a speaker protection control signal (SPKPROT), a first latch 306 for receiving the offset control signal at node 305, a first logic gate 308 for receiving the play control signal at node 307, the offset control signal at node 305, and the speaker protection control signal SPKPROT, a second logic gate 310 coupled to the first latch 306 for receiving the play control signal and the speaker protection control signal, a second latch 312 coupled to the first logic gate 308 for providing the forced mute signal FORCEMUTE, and a third latch 314 coupled to the second logic gate 31 o and to the intermediate node 309.

The first, second, and third latches 306, 312, and 314 are D-type flip-flops clocked by the amplifier control signal (ON), wherein the inverted Q output is coupled to the D-input. CP is the positive edge triggered clock input and CD is the clear active low input, which clears the output when it is low. The first and second logic gates 308, 310 are three-input NAND gates.

The speaker protection method of the present invention is described below.

The power amplifier generates two internal signals, namely SPKPROT and FORCEMUTE.

The MCU turns on the amplifier in mute mode, and SPKPROT signal is latched high.

After about one second, the MCU sends a PLAY command to the amplifier, and makes sure no signal is applied to the inputs of the amplifier for about 100 ms.

After the MUTE to PLAY transition time (which is about 40 ms) the amplifier checks the output offset status using internal comparators.

If there is high offset and SPKPROT=1, FORCEMUTE is latched high and the amplifier forces itself back into MUTE mode, and SPKPROT remains at a logic one. A bit of an I²C bus output is set to a logic one to inform the speaker system that the speaker protection is triggered. The MUTE mode is locked and can be reset only when MCU turns off the amplifier by the I²C bus.

If there is no offset greater than two volts, and SPKPROT=1, FORCEMUTE is latched low which allows amplifier to work in PLAY mode and SPKPROT is reset to a logic zero, which keeps the new speaker protection function inactive in order not to mute the output in case an input signal is applied.

The new embedded speaker protection according to the present invention requires the MCU to turn on the audio power amplifier in a proper sequence. The MCU should first turn on the device in MUTE condition and, after a suitable time for the device to fully work, send a PLAY command to the device and make sure there is no input signal applied to any of the inputs for at least 100 ms.

If the MCU turns on the amplifier directly to play mode without enough setting time for the amplifier to be stable, the speaker protection mechanism of the present invention may not work.

If there is external signal applied to any of the amplifier inputs during this turn-on phase, the new speaker protection mechanism may give an improper mute instruction to the amplifier itself.

Referring now to FIG. 4, the method 400 of operating a speaker system including a speaker coupled to an amplifier, comprises turning on the amplifier in a mute mode 402, after a first delay period, issuing a play command to the amplifier to place the amplifier in a play mode, but without an input signal during a second delay period 404, and performing a speaker offset detection 406 during the second delay period, wherein, if there is an offset, then the amplifier is forced back into the mute mode 412, and if there is no offset, then the amplifier is allowed to continue to operate in the play mode 410. A microprocessor issues a command to place the amplifier in the mute mode and the play mode. Forcing the amplifier back into the mute mode is accomplished by the dedicated digital circuit in the amplifier, which is shown in FIG. 3. The offset detection comprises a detection of a threshold offset greater than about two volts. The method of the present invention further comprises issuing a speaker protection control signal or command if an offset is detected.

The results of the speaker protection method of the present invention is verified in FIG. 5, which shows that the device is set to PLAY about one second after turn-on. After the MUTE to PLAY transition the device detects a high offset which is above two volts and then mutes itself. Note that speaker output terminals 502 and 504 show a glitch when the offset is detected, which is quickly suppressed before any damage can occur to the speaker (or speakers).

Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed. 

What is claimed is:
 1. A circuit comprising: an amplifier with an output configured to be coupled to a speaker; an offset comparator with an input coupled to the output of the amplifier, the offset comparator configured to provide an offset control signal; and a digital circuit having a first input coupled to an output of the offset comparator, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal for controlling the amplifier.
 2. The circuit of claim 1, wherein the digital circuit is embedded in the amplifier.
 3. The circuit of claim 1, wherein the digital circuit comprises: an intermediate node for providing a speaker protection control signal; a first latch coupled to the first input coupled to receive the offset control signal; a first logic gate coupled to the input coupled to receive the play control signal, the first logic gate also coupled to receive the offset control signal and the speaker protection control signal; a second logic gate coupled to the first latch to receive the play control signal and the speaker protection control signal; a second latch coupled to the first logic gate to provide the forced mute signal; and a third latch coupled to the second logic gate and to the intermediate node.
 4. The circuit of claim 3, wherein the first, second, and third latches are each controlled by a common amplifier control signal.
 5. The circuit of claim 3, wherein the first, second, and third latches each comprise a D-type flip flops.
 6. The circuit of claim 5, wherein each D-type flip flop comprises an inverted output coupled to a D input.
 7. The circuit of claim 3, wherein the first logic gate and the second logic gate each comprise a three-input NAND gate.
 8. The circuit of claim 3, wherein the first logic gate and the second logic gate each comprise a three-input AND gate.
 9. The circuit of claim 1, wherein the first input comprises an offset indication input node, the second input comprises a mute control output node and the third input comprises a play control signal input node, and wherein the digital circuit comprises: an intermediate node configured to carry a speaker protection control signal; a first latch with an input coupled to the offset indication input node; a first comparison circuit with an output coupled to the mute control output node, the first comparison circuit having inputs coupled to the play control signal input node, the offset indication input node, and the intermediate node; and a second comparison circuit with an output coupled to the intermediate node, the second comparison circuit having inputs coupled to the play control signal input node, an output of the first latch, and the intermediate node.
 10. The circuit of claim 9, wherein the first comparison circuit comprises a first logic gate and wherein the second comparison circuit comprises a second logic gate.
 11. The circuit of claim 10, wherein the first comparison circuit further comprises a second latch coupled to an output of the first logic gate and wherein the second comparison circuit further comprises a third latch coupled to an output of the second logic gate.
 12. The circuit of claim 11, wherein the first, second, and third latches are each controlled by a common amplifier control signal.
 13. The circuit of claim 11, wherein the first, second, and third latches each comprise a D-type flip flop that comprises an inverted output coupled to a D input.
 14. The circuit of claim 10, wherein the first logic gate and the second logic gate each comprise a three-input NAND gate.
 15. A circuit comprising: an amplifier with an output configured to be coupled to a speaker; an offset comparator with an input coupled the output of the amplifier to the speaker, the offset comparator configured to provide an offset control signal; means for generating a speaker control signal based upon a play control signal and an earlier value of the offset control signal; and means for generating a force mute signal based on the offset control signal, the play control signal and the generated speaker control signal.
 16. A speaker system comprising: a speaker; an amplifier with an output coupled to the speaker, the amplifier including a digital circuit embedded therein, the digital circuit comprising having a first input, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal; an offset comparator with an input coupled the output of the amplifier and an output coupled to the first input of the digital circuit embedded in the amplifier, the offset comparator configured to provide an offset control signal; and a microprocessor coupled to the digital circuit embedded in the amplifier to receive the forced mute signal for controlling the amplifier.
 17. The system of claim 16, wherein the digital circuit embedded in the amplifier comprises: an intermediate node for providing a speaker protection control signal; a first latch coupled to the first input coupled to receive the offset control signal; a first logic gate coupled to the input coupled to receive the play control signal, the first logic gate also coupled to receive the offset control signal and the speaker protection control signal; a second logic gate coupled to the first latch to receive the play control signal and the speaker protection control signal; a second latch coupled to the first logic gate to provide the forced mute signal; and a third latch coupled to the second logic gate and to the intermediate node.
 18. The system of claim 17, wherein the first, second, and third latches each comprise a D-type flip flops that comprises an inverted output coupled to a D input, and wherein the first logic gate and the second logic gate each comprise a three-input AND gate.
 19. The system of claim 16, wherein the first input comprises an offset indication input node, the second input comprises a mute control output node and the third input comprises a play control signal input node, and wherein the digital circuit comprises: an intermediate node configured to carry a speaker protection control signal; a first latch with an input coupled to the offset indication input node; a first comparison circuit with an output coupled to the mute control output node, the first comparison circuit having inputs coupled to the play control signal input node, the offset indication input node, and the intermediate node; and a second comparison circuit with an output coupled to the intermediate node, the second comparison circuit having inputs coupled to the play control signal input node, an output of the first latch, and the intermediate node.
 20. The system of claim 19, wherein the first comparison circuit comprises a first logic gate and a second latch coupled to an output of the first logic gate; wherein the second comparison circuit comprises a second logic gate and a third latch coupled to an output of the second logic gate; wherein the first, second, and third latches are each controlled by a common amplifier control signal; wherein the first, second, and third latches each comprise a D-type flip flop; and wherein the first logic gate and the second logic gate each comprise a three-input NAND gate. 